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[MPI] arban

Description: 这是一个用verilog实现的除法器代码。-This is a realization of the use verilog divider code.
Platform: | Size: 1024 | Author: arban | Hits:

[MiddleWare] fre_division

Description: 使用verilog编写分频器，包括奇分频和偶分频，可以进行任意奇偶分频-Prepared using the Verilog divider, including odd and even sub-sub-band frequency can be arbitrary odd-even frequency
Platform: | Size: 2048 | Author: 牧云 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 介绍了除法器的设计，采用verilogHDL语言，利用modelsim仿真验证，压缩包中包含了流程图-Introduced the divider design, using verilogHDL language, the use of ModelSim simulation, compressed package that contains a flow chart
Platform: | Size: 83968 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] div2

Description: 32位除法器 被除数和除数均为16位整数，16位小数 商为32位整数，16位小数 余数为16位整数，16位小数 Verilog HDL 代码-32 divider dividend and divisor are 16-bit integer, decimal 16 for the 32-bit integer, 16-bit decimal number more than 16 integer, 16-bit decimal Verilog HDL code
Platform: | Size: 1024 | Author: 李春阳 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 基于srt-2算法，利用verilog实现16位定点无符号数除法器（除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成）-Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into)
Platform: | Size: 3072 | Author: 刘蒲霞 | Hits:

[VHDL-FPGA-Verilog] Frequency_divider

Description: 用VERILOG HDL实现的任意 频率分频器源代码，是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure
Platform: | Size: 134144 | Author: 洪磊 | Hits:

[VHDL-FPGA-Verilog] 32_16div

Description: 这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction
Platform: | Size: 1024 | Author: 郭勇谅 | Hits:

[VHDL-FPGA-Verilog] div

Description: 除法器实验 verilog CPLD EPM1270 源代码-Experimental divider verilog CPLDEPM1270 source code
Platform: | Size: 117760 | Author: 韩思贤 | Hits:

[VHDL-FPGA-Verilog] div16

Description: 十六位的除法器，采用verilog hdl-16 of the divider using verilog hdl
Platform: | Size: 3072 | Author: 江浩 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 基于Verilog的除法器设计，可以直接在Q2里面运行哦~-Verilog-based design of the divider, which can be run directly in Q2 Oh ~
Platform: | Size: 1024 | Author: 谢玮霖 | Hits:

[VHDL-FPGA-Verilog] devider

Description: a divider design based on verilog language
Platform: | Size: 2048 | Author: Xiao Yang | Hits:

[ELanguage] 32bit

Description: multiplier and divider verilog codes
Platform: | Size: 6144 | Author: damasqas | Hits:

[VHDL-FPGA-Verilog] divide

Description: It is n-bit sequential divider in verilog language
Platform: | Size: 1024 | Author: Lisha | Hits:

[VHDL-FPGA-Verilog] divider

Description: verilog divider hardware
Platform: | Size: 29696 | Author: dumbmage | Hits:

[VHDL-FPGA-Verilog] div_n

Description: verilog占空比50奇偶任意 奇偶任意分频器！包括测试代码-verilog random duty cycle of 50 odd parity arbitrary divider! Including test code
Platform: | Size: 1024 | Author: 龚俊杰 | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 一些关于Verilog分频器设计.doc-Verilog divider design. Doc
Platform: | Size: 9216 | Author: 左会刚 | Hits:

[VHDL-FPGA-Verilog] divider

Description: verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
Platform: | Size: 2048 | Author: 韩冰 | Hits:

[VHDL-FPGA-Verilog] verilog-divider-code

Description: Verilog编写的分频器程序，包括偶数分频和奇数分频，作为参考。-verilog divider code
Platform: | Size: 2048 | Author: duwenjian | Hits:

[VHDL-FPGA-Verilog] verilog--divide-programs

Description: verilog任意分频程序，包括奇数倍分频和偶数倍分频，占空比为50 ，QuartusII上验证程序有效-verilog every divide programs, including an odd multiple divider and even multiple frequency, duty cycle 50 , the QuartusII on the verification process
Platform: | Size: 578560 | Author: ni husheng | Hits:

[Other] divider

Description: verilog的除法器 有多重方法 很适合初级者阅读-verilog divider multiple method is very suitable for beginners to read
Platform: | Size: 1097728 | Author: ran | Hits:
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